This invention relates to methods of etching a semiconductor substrate, with particular, but by no means exclusive, reference to the etching of a semiconductor substrate to reveal one or more features buried in the substrate such as vias. A claim of priority is made to United Kingdom (UK) Patent Application No. 1406135.2, filed on 4 Apr. 2014, the disclosure of which is incorporated herein by reference in its entirety.
Through Silicon Vias (TSV) are vertical electrical connections typically filled with copper which extend vertically through silicon wafers. TSVs are important components in the creation of 3D packages and 3D integrated circuits. During the manufacturing process, it is typical for the electrically conductive via material to be protected with an outer liner formed from a suitable protective material such as a silicon oxide.
In the manufacturing process, the TSVs, including the protective layers, are initially buried within a silicon substrate. Via reveal etching involves etching the silicon substrate so as to reveal the upper tips of the TSVs. To achieve optimal results with a via reveal etch, it is considered necessary to satisfy three criteria. Firstly, the etch should achieve a high etch rate with good uniformity. Secondly, it is necessary to achieve a high silicon to oxide etch selectivity in order to maintain the oxide protective liner on the TSV. This prevents exposure of the underlying electrically conducted material (such as copper) to the process gases and plasma which are ubiquitously used to achieve the etch. A silicon to oxide selectivity of greater than 100:1, and preferably greater than 150:1, is considered desirable for this purpose. Thirdly, the final silicon surface achieved at the end of the etch process should be as smooth as possible. It is necessary to achieve a smooth surface in order to prevent problems in subsequent steps of the manufacturing process, for example optical inspection failures due to the wafer having unacceptable properties of reflection, alignment problems, and problems associated with laser dicing. In practice, there is a fine balance between surface roughness and etch selectivity. More specifically, processes and process parameters which can result in good selectivity can also result in a high level of surface roughness. The reverse is also true. For example, it is known that the use of a high bias power during plasma etching can achieve low silicon roughness levels; however, this results in poor oxide selectivity. It is particularly difficult to balance these different criteria in a continuous process. However, continuous processes are desirable in terms of efficiency. A further problem is that surface roughness increases with the depth of silicon removed.